SN74AUP2G125 Low Power Dual Bus Buffer Gate

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            SN74AUP2G125 Low Power Dual Bus Buffer Gate
                    Low-power dual bus buffer gate with 3-state outputs
    

SN74AUP2G125 Low Power Dual Bus Buffer Gate The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity.

The SN74AUP2G125 is a dual bus buffer gate designed for 0.8 V to 3.6 V V_CC operation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, output-enable should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Features and Benefits

Available in the Texas Instruments NanoFree™ package
Low static-power consumption (I_CC = 0.9 µA max)
Low dynamic-power consumption (C_pd = 4 pF typ at 3.3 V)
Low input capacitance (C_I = 1.5 pF Typ)
Low noise: overshoot and undershoot <10% of V_CC
Input-disable feature allows floating input conditions
I_off supports partial-power-down mode operation
Input hysteresis allows slow input transition and better switching noise Immunity at input
Lowest-power family
Extends battery life for portable applications
Can interface with next generation processors